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European UnionNon-profit, Private Business, Research Institution, Public Institution

DIGITAL-JU-CHIPS-2025-SG-SSOI

DIGITAL JU Simple Grants

Funding Amount

€1.0M - €3.0M

Deadline

20/11/2025

Eligible Organization Types

Non-profit, Private Business, Research Institution, Public Institution

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What is the DIGITAL-JU-CHIPS-2025-SG-SSOI Call?

Grant Description
This call seeks to establish a European open accelerator for strained silicon on insulator technology, enabling access to advanced FD-SOI process development and manufacturing. Funded projects will develop industrial-grade SOI substrates with low defect densities, refine strain engineering for 7 nm FD-SOI, optimize epitaxial growth, wafer bonding and defect reduction processes, and standardize process design kits. The aim is to strengthen Europe’s semiconductor production capacity, foster collab...
Required Results for Successful Funding

Expected Outcomes

A sustainable European accelerator for s SOI technology accessible to all stakeholders; standardized PDKs enabling designers to optimize system-level architectures and ensure readiness for 7 nm FD-SOI high-volume manufacturing by 2030; industrial-scale production of low-defect s SOI wafers with improved yields; generation of new intellectual property and bolstered European production capacity in s SOI technologies; enhanced synergies with FD-SOI and other Chips JU pilot lines to strengthen Europe’s semiconductor innovation leadership; and a skilled European workforce trained in s SOI substrate integration and advanced manufacturing processes.
Funded areas

Scope Requirements

Proposals must address all technological steps to bring s SOI substrates to industrial scale, including: 1) Development of industrial-grade s SOI substrates with ultra-low defect densities to enhance electron mobility and meet 7 nm FD-SOI performance targets. 2) Refinement of strain engineering to introduce uniform global strain balancing strained NMOS and relaxed PMOS transistors. 3) Process integration and optimization compatible with current semiconductor manufacturing (advanced epitaxial growth, wafer bonding, defect reduction techniques). 4) Collaboration across the semiconductor ecosystem, connecting with other Chips JU pilot lines, design platforms and competence centres.
Additional Conditions for Applicants

Special Conditions

Admissibility: comply with page limits, layout and annex rules (Appendix 6-v4 of the Chips JU Work Programme). Eligibility: applicants from eligible countries meeting financial and operational capacity, and exclusion criteria. Submission: single-stage via Funding & Tenders Portal (8 July 2025–20 November 2025 17:00 Brussels time). Use prescribed templates (application form Part B, national funding table, ownership declaration) and adhere to DEP Reg 2021/964, EU Financial Reg 2024/2509, EU Grants AGA rules. Evaluation per defined processes, award criteria, scoring thresholds and timelines. Budget per grant: €1 million–€3 million. Legal and financial set-up as per Call documents.
Important dates

Open from: 08/07/2025

Deadline:20/11/2025

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